1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a synchronous semiconductor memory device capturing an external signal in synchronism with a clock signal given periodically from outside the device. More particularly, the present invention relates to a test mode circuit in a synchronous dynamic random access memory (hereinafter referred to as SDRAN) using a data strobe signal (DQS) for capturing data.
2. Description of the Background Art
Although a dynamic random access memory (DRAM) used as a main memory has acquired a high speed in operation, but still, its operating speed cannot catch up an operating speed of a microprocessor (MPU). For this reason, it has been often said that an access time and a cycle time of a DRAM become bottlenecks, thereby reducing performance of all the system. In recent years, there has been proposed a double data rate SDRAM (DDR SDRAM) operating in synchronism with a clock signal as a main memory for a high speed MPU.
As a higher speed operation becomes possible, a test for confirming operation of a semiconductor memory device is harder to perform.
FIG. 20 is a diagram for describing a test for confirming functions of a semiconductor memory device.
Referring to FIG. 20, a semiconductor memory device 712 is confirmed on its operation by a tester 700. Tester 700 includes: a timing generator 702; a signal generator 704 generating an input signal to semiconductor memory device 712 according to an output of timing generator 702; and a driver 706 driving an input node of semiconductor memory device 712 according to an output of signal generator 704. Driver 706 gives semiconductor memory device 712 complementary clock signals extCLK and ext/CLK, control signals /RAS and /CAS, complementary strobe signals DQS and /DQS, and a data input signal DIN.
Semiconductor memory device 712 outputs a data output signal QOUT according to a signal given from tester 700.
Tester 700 includes: a comparator 710 performing a level determination on a signal outputted from the semiconductor memory device 712 with a predetermined threshold value; and a determination section 708 performing determination by comparing an output from comparator 710 with an expected value pattern at a timing given from timing generator 702.
FIG. 21 is an operating waveform diagram for describing input and output waveforms in a standardized operation of DDR SDRAM.
In FIG. 21, there is shown a write or read operation for consecutive 4 data (a total of 32 bits of 8xc3x974) in an SDRAM capable of inputting and outputting of 8 bit data (byte data) at data input/output terminals DQ0 to DQ7. The number of bits of data read out consecutively is referred to a burst length and the burst length can be usually changed by setting of a mode register in a DDR SDRAM.
Referring to FIG. 21, at a time point t1, control signals from the outside (a row address strobe signal /RAS, a column address strobe signal /CAS, an address signal Add. and so on) are captured at a rise edge of the clock signal extCLK. Since row address strobe signal /RAS is at L level in an active state, address signal Add. at this time is captured as a row address Xa. Note that address signal Add. includes address signals A0 to A10 and a bank address signal BA.
At a time point t2, the column address strobe signal /CAS goes to L level in an active state and captured into the interior of the DDR SDRAM in synchronism with a rise of clock signal ext.CLK. Address signal Add at this time is captured as a column address Yb. A column or row select operation is performed in DDR SDRAM according to row address Xa and column address Yb captured.
D/Q shows data signals DQ0 to DQi inputted and outputted from an input/output terminal. After predetermined clock cycles (in FIG. 21, 3.5 clock cycles) passes away from a fall of row strobe address /RAS to L level, first data q0 is outputted at a time point t4 and data q1 to data q3 are consecutively outputted, following data q0.
Outputting the data q0 to q3 is performed in response to a crossing point between clock signal extCLK and clock signal ext/CLK. In order to enable high speed data transfer, data strobe signal DQS is outputted in phase with output data.
Note that at a rise edge of clock signal extCLK, which is a time point t3, control signals /RAS and /WE are set to L level and rewrite (precharge) to a memory cell is performed.
Signal waveforms at a time point t5 or later show a write operation. At time point t5, row address Xc is captured. At a time point t6, column address strobe signal /CAS and write enable signal /WE are both set to L level in an active state and at the time, column address Yd is captured at a rise edge of clock signal extCLK. Data d0 having been given at the time is captured as first write data. In response to falls of row address strobe signal /RAS and column address strobe signal /CAS, row and column select operations are performed inside DDR SDRAM. Hereinafter, input data dl to d3 are sequentially captured in synchronism with data strobe signal DQS and written into respective corresponding memory cells.
As an operating speed of a semiconductor device increases, the accuracy of a tester in test on confirmation of its operation becomes problematic. In tester 700 described in FIG. 20, calibration is performed in order to keep a state of the tester constant. For example, this is because, if shifts in timing exist between plural control signals given to a semiconductor memory device from the tester, an inspection yield decreases.
Generally speaking, testers used in mass production or the like are each operated on many of devices simultaneously. Such a tester performing simultaneous measurement on many devices suffers from its lowered accuracy due to large numbers of driver pins and comparator pins. Contrary to this, most of testers for use in evaluation of a device in the development stage, where a small number of devices can be simultaneously measured therewith, have good accuracy due to the small number of measured devices. Therefore, it is conceived that a device with known characteristics having been measured by a high accuracy tester is used for calibration of a tester for mass production operative on simultaneous measurement of many of devices. That is, in this case, a standard device having known measurements is used and adjustments on a low accuracy tester are performed so as to output the same value as from the standard device.
For example, in a case of DDR SDRAM, data signal DQ is captured with data strobe signal DQS. Therefore, a set-up time and a hold time of data, which has been measured with a high accuracy tester, are measured by the low accuracy tester and phase matching on the low accuracy tester is performed. Then, a difference in output timing between a driver of a tester outputting data strobe signal DQS and a driver of a tester outputting data signal DQ can be narrowed.
However, there exist items that cannot be matched only by adjustments on device characteristics.
FIG. 22 is an operating waveform diagram showing relationships among clock signals CLK and /CLK, data strobe signals DQS and /DQS and data signal DQ in an ideal case.
Referring to FIG. 22, clock signal CLK and clock signal /CLK are crossed at a point of just a half amplitude of the waveforms. This applies to a relationship between data strobe signal DQS and data strobe signal /DQS in a similar manner.
FIG. 23 is an operating waveform diagram for describing a case where there arises a shift between waveforms of complementary signals.
Referring to FIG. 23, there is shown a case where clock signal /CLK lags behind clock signal CLK by some in respect to phase. Similar to this, data strobe signal /DQS lags behind data strobe signal DQS by some in respect to phase.
In a case where as shown in FIG. 23, clock signals CLK and /CLK are shifted from each other in respect to phase, the shift cannot be detected using a standard device whose characteristics have been measured. Similar to this, the shift between data strobe signals DQS and /DQS complementary to each other cannot also be detected. In this situation, calibration is performed in a state of phase shift, resulting in lowered measurement accuracy. If not so, different values than ones in real performance of a device are measured. That is, an error arises in measurement.
It is accordingly an object of the present invention to provide a semiconductor memory device with a test mode capable of performing efficient calibration of a measuring apparatus.
The present invention will be summarized this way: the present invention is directed to a semiconductor device with a normal mode and a test mode as operation modes, and including: an internal circuit; a phase comparator circuit; and an output buffer circuit.
The internal circuit operates according to first and second input signals in the normal mode. The phase comparator circuit compares the first and second input signals with each other in respect to phase in the test mode. The output buffer circuit outputs an output of the phase comparator circuit to outside the semiconductor device in the test mode.
According to another aspect of the present invention, the present invention is directed to a semiconductor device with a normal mode and a test mode as operation modes, including: a clock generator circuit and an input/output circuit.
The clock generator circuit outputs an internal clock signal according to an external clock signal. The clock generator circuit delays the external clock signal by a delay amount corresponding to a phase difference between the internal clock signal and the external clock signal to output the delayed external clock signal as the internal clock signal in the normal mode, while delaying the external clock signal by a fixed delay amount to output the delayed external signal as the internal clock in the test mode. The input/output circuit supplies and receives signals to and from outside the semiconductor device according to the internal clock signal.
Therefore, a main advantage of the present invention is in that since a result of comparison of two input signals with each other in respect to phase is outputted to outside the semiconductor device in the test mode, a tester can perform its own high accuracy calibration using the result of comparison.
Another advantage of the present invention is in that since a delay amount of a DLL circuit is fixed, a fluctuation in access time generated by the DLL circuit as a cause can be suppressed, thereby enabling calibration of a high accuracy tester.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.